This invention relates to connections in electronic assemblies and more particularly to a surface mounted integrated circuit chip carrier.
Surface mounted devices (SMDs) are electronic components that are designed to sit on the surface of a printed wiring board (PWB) or another compatible substrate. Components such as resistors, capacitors, diodes, transistors and integrated circuits (IC) may be designed as SMDs and, as such, have either no leads but flat interfacing surfaces or very short leads. The interfacing surfaces or the short leads of these components serve as contact pads which align with corresponding electrical connections on a PWB.
Typically the components are mounted or fabricated within a ceramic or plastic carrier to provide a desired configuration having contact pads on the external surface of the carrier which are electrically connected to the component contained therein.
The advantages of SMDs are numerous. The size of these devices may be 30 to 60% smaller than the traditional leaded components they replace. The holes within the PWBs which accept the leads of leaded components are no longer necessary when utilizing SMDs. For this reason, not only may SMDs be mounted closer together, but SMDs may also be mounted on each side of a PWB. Because of these factors, the overall size and weight of a populated PWB is less than that of a PWB using leaded components.
One specific type of an SMD is an IC chip carrier. Because of the frailty and the inherently small size of an IC chip, the IC chip is typically mounted in a chip carrier which provides structural reinforcement for the chip and also provides a means for making external electrical connections to the IC chip. A chip in a sealed ceramic carrier has the further advantage of providing to the chip hermetic isolation from the outside environment.
Utilizing current chip carrier designs, problems arise when the IC chip is a high power device which generates substantial amounts of heat. First of all SMD technology the size of the chip carrier may be reduced but the necessary heat transfer from the IC chip remains the same. For this reason a chip carrier design is required that is more conducive to transferring heat from the IC chip, thereby permitting heat transfer from an IC chip within a smaller chip carrier.
Secondly, in the past decoupling capacitors used in conjunction with the IC chip were mounted elsewhere on the PWB and electrically connected to the IC chip or a capacitor was mounted to the exterior of the chip carrier, thereby requiring external connections from the chip carrier to the decoupling capacitor even though the decoupling capacitor was electrically connected only to the IC chip.
Thirdly, ceramic materials are used in the fabrication of the chip carrier and associated with the use of ceramic is some degree of shrinkage during the chip carrier fabrication. This becomes critical with SMD chip carriers because the contact pads on the outside of the carrier must be in a precise pattern to align with mating pads on the PWB. As the size of the distance between contact pads is reduced, precise patterns become even more critical.
FIG. 1 shows a cavity-up chip carrier with a pad grid array 10. The chip carrier 10 is comprised of a body 15 having an upwardly facing cavity 20. An IC chip 25 is mounted at the base of the cavity 20. The body 15 configuration is such that within the cavity 20 are a series of ledges 30. From the surface of a ledge 30, electrical strips known as traces 31 extend through the body 15 to vias 32 which then extend downward and are distributed within the body 15 such that each via 32 emerges through the bottom of the body 15 to connect with electrical contact pads 35 of the chip carrier 10. Bonding wires 34 extend from connections on the IC chip 25 to corresponding traces 31 on the ledge 30 of the body 15. With this arrangement, each chip connection from the IC chip 25 is electrically connected to a pad 35 at the bottom of the body 15. As a protective measure, a package lid 40 is secured to the body 15 to fully enclose the cavity 20. The arrangement of the pads 35 at the bottom of the body 15 may form a grid array which extends over the entire area of the bottom of the body 15 or may form a pad arrangement limited to a single row of pads around the perimeter of the body 15. With the number of connections from an IC chip remaining approximately constant and the size of chip carriers steadily reducing, the arrangement of pads in a single row around the perimeter of the body 15 may become impossible because of the necessity for a minimum pad 35 size and therefore it becomes necessary to utilize pads in a grid array arrangement to take full advantage of the area at the bottom of the body 15.
The chip carrier 10 is secured to a PWB 45 which has on its surface electrical interconnect pads (not shown) to which the pads 35 on the chip carrier 10 are aligned. The pads 35 may be secured to the PWB 45 using solder at each carrier pad/PWB interconnect pad interface or may be secured utilizing an external mechanical means to secure the chip carrier 10 to the PWB 45. A decoupling capacitor 50 typically associated with IC chips is attached to the PWB 45 at a proximate location to the chip carrier 10 and electrical connections are made between the decoupling capacitor 50 and the chip carrier 10. In some instances the decoupling capacitor 15 is externally mounted upon the chip carrier 10. Note that an electronic component other than a decoupling capacitor may also be mounted relative to the chip carrier in the same manner as that just described.
The body 15 may be made ceramic and as such during fabrication experiences shrinkage. Because of the tolerance required to fabricate a chip carrier 10 with precisely located pads 35, great care must be taken in designing and fabricating the body 15 such that after shrinkage, the location of the pads will be known. While the shrinkage of the ceramic material used to construct the body is uniform and there is a predictable error range of shrinkage, accurate determination of the locations of the pads 35, after the base has been fabricated, is very difficult.
Furthermore, oftentimes the IC chip 25 will generate substantial amounts of heat that must be effectively removed in order to avoid damage to the chip 25. Typically, the PWB 45 has associated with it a heat sink 55 secured to the PWB 45 through an adhesive interface 60. Heat generated by the IC chip 25 is first conducted through the body 15 and then conducted through each of the pads 35 to the associated PWB interconnect pads at the PWB 45. From here, the heat passes through the PWB 45 past an adhesive interface 60 to a heat sink 55, as indicated by arrows 57, where the heat is removed. For high power IC chips, this heat transfer path may not be adequate to remove all of the generated heat.
It is an object of this invention to provide a chip carrier design that effectively removes heat from a high powered IC chip.
It is another object of this invention to provide a chip carrier design in which the decoupling capacitors may be located directly within the chip carrier body.
It is still another object of this invention to provide a chip carrier design in which the locations of the external electrical contact pads on the chip carrier are known with precision.